1. Field of the Invention
The invention relates to a process for producing an integrated multi-layer insulator memory cell via silicon gate technology with a self-adjusting overlapping polysilicon contact as well as the so-attained integrated memory cell.
2. Prior Art
Currently, polysilicon-gate technology is used with preference in the production of MOS components, and particularly for memory circuits. In this technology, the gate electrodes of field effect transistors and conductor paths for connection of these electrodes are formed from polysilicon. The main advantage of this technology, in comparison to one in which the electrodes and conductor paths are composed of aluminum, consist in that the disturbing gate-source overlap capacitance and gate-drain overlap capacitance can be kept very small and an additional "conductor path" plane is provided in the form of the polysilicon layer.
The construction of a MNOS component differs from that a MOS component in that the gate dielectric consists of two layers, an upper layer composed of silicon nitride (Si.sub.3 N.sub.4) and a lower layer composed of silicon dioxide (SiO.sub.2). MNOS technology is used for electrically reprogrammable fixed work stores. These stores or memories are smaller and require only one transistor per memory cell which results in high packing density.
"IEEE Transactions On Electron Devices", Vol Ed-b 24, No. 5, May 1977, pages 584-586 discloses a Si-gate-MNOS structure in an example of a capacitance produced in a P-type silicon substrate. In this arrangement, the production of an oxynitride layer by the oxidation of a silicon nitride surface prevents an undesired charge carrier injection from the silicon-gate electrode, which would lead to the disintegration and partial erasure of the stored information. In the following specification and claims, this layer will be referred to as a "blocking" layer.